PIC24F08KL301-I/SS【PDF 194/260 页】IC MCU 16BIT 8KB FLASH 20-SSOP

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Sheet目录3882

190页 191页 192页 193页 [194页]195页 196页 197页 198页

PIC24F16KL402

FAMILY

DS3

1037B-page

rochip

chnology

TABLE 4-8:

MSSP REGISTER MAP

File Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

SSP1BUF

0200

—

MSSP1 Receive Buffer/Transmit Register

00xx

SSP1CON1

0202

—

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000

SSP1CON2

0204

—

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

0000

SSP1CON3

0206

—

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

0000

SSP1STAT

0208

—

—SMP

CKE

D/A

R/W

0000

SSP1ADD

020A

—

MSSP1 Address Register (I2C Slave Mode)

MSSP1 Baud Rate Reload Register (I2C Master Mode)

0000

SSP1MSK

020C

—

MSSP1 Address Mask Register (I2C Slave Mode)

00FF

SSP2BUF(1)

0210

—

MSSP2 Receive Buffer/Transmit Register

00xx

SSP2CON1(1)

0212

—

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000

SSP2CON2(1)

0214

—

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

0000

SSP2CON3(1)

0216

—

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

0000

SSP2STAT(1)

0218

—

—SMP

CKE

D/A

R/W

0000

SSP2ADD(1)

021A

—

MSSP2 Address Register (I2C Slave Mode)

MSSP2 Baud Rate Reload Register (I2C Master Mode)

0000

SSP2MSK(1)

021C

—

MSSP2 Address Mask Register (I2C Slave Mode)

00FF

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

These bits and/or registers are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X family devices; read as ‘0’.

TABLE 4-9:

UART REGISTER MAP

File

Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

U1MODE

0220

UARTEN

—

USIDL

IREN

RTSMD

—

UEN1

UEN0

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL1

PDSEL0

STSEL

0000

U1STA

0222

UTXISEL1 UTXINV UTXISEL0

—

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL1 URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

0110

U1TXREG

0224

—

UART1 Transmit Register

xxxx

U1RXREG

0226

—

UART1 Receive Register

0000

U1BRG

0228

Baud Rate Generator Prescaler Register

0000

U2MODE

0230

UARTEN

—

USIDL

IREN

RTSMD

—

UEN1

UEN0

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL1

PDSEL0

STSEL

0000

U2STA

0232 UTXISEL1 UTXINV UTXISEL0

—

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL1 URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

0110

U2TXREG

0234

—

UART2 Transmit Register

xxxx

U2RXREG

0236

—

UART2 Receive Register

0000

U2BRG

0238

Baud Rate Generator Prescaler Register

0000

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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